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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
| Date : Wed Dec 02 15:16:42 2015
| Host : FS running 64-bit Service Pack 1 (build 7601)
| Command : report_timing_summary -file timing_impl.log
| Design : system_top
| Device : 7z020-clg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 7 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 30 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.541 0.000 0 13325 0.037 0.000 0 13325 1.100 0.000 0 5689
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk_fpga_0 {0.000 5.000} 10.000 100.000
clk_fpga_1 {0.000 2.500} 5.000 200.000
mmcm_clk_0_s {0.000 3.367} 6.735 148.485
mmcm_fb_clk_s {0.000 27.500} 55.000 18.182
i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1 {0.000 2.500} 5.000 200.000
clk_out1_system_sys_audio_clkgen_0 {0.000 40.690} 81.380 12.288
clkfbout_system_sys_audio_clkgen_0 {0.000 22.500} 45.000 22.222
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk_fpga_0 2.047 0.000 0 10676 0.049 0.000 0 10676 2.501 0.000 0 4646
clk_fpga_1 1.100 0.000 0 2
mmcm_clk_0_s 0.541 0.000 0 1355 0.055 0.000 0 1355 2.387 0.000 0 997
mmcm_fb_clk_s 45.000 0.000 0 3
i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1 1.100 0.000 0 1
clk_out1_system_sys_audio_clkgen_0 78.403 0.000 0 61 0.037 0.000 0 61 39.440 0.000 0 37
clkfbout_system_sys_audio_clkgen_0 42.845 0.000 0 3
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
clk_out1_system_sys_audio_clkgen_0 clk_fpga_0 7.881 0.000 0 4
clk_fpga_0 clk_out1_system_sys_audio_clkgen_0 79.176 0.000 0 5
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** clk_fpga_0 clk_fpga_0 2.596 0.000 0 1053 0.334 0.000 0 1053
**async_default** mmcm_clk_0_s mmcm_clk_0_s 2.115 0.000 0 180 0.290 0.000 0 180
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: clk_fpga_0
To Clock: clk_fpga_0
Setup : 0 Failing Endpoints, Worst Slack 2.047ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.049ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 2.501ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.047ns (required time - arrival time)
Source: i_system_wrapper/system_i/sys_ps7/inst/PS7_i/MAXIGP0ACLK
(rising edge-triggered cell PS7 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_wdata_reg[2]/D
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 7.610ns (logic 1.450ns (19.053%) route 6.160ns (80.947%))
Logic Levels: 0
Clock Path Skew: -0.157ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.759ns = ( 12.759 - 10.000 )
Source Clock Delay (SCD): 3.031ns
Clock Pessimism Removal (CPR): 0.115ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.193 1.193 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4650, routed) 1.737 3.031 i_system_wrapper/system_i/sys_ps7/inst/M_AXI_GP0_ACLK
PS7_X0Y0 PS7 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/MAXIGP0ACLK
------------------------------------------------------------------- -------------------
PS7_X0Y0 PS7 (Prop_ps7_MAXIGP0ACLK_MAXIGP0WDATA[2])
1.450 4.481 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/MAXIGP0WDATA[2]
net (fo=41, routed) 6.160 10.641 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/s_axi_wdata[2]
SLICE_X22Y48 FDCE r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_wdata_reg[2]/D
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.088 11.088 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.179 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4650, routed) 1.579 12.759 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/s_axi_aclk
SLICE_X22Y48 FDCE r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_wdata_reg[2]/C
clock pessimism 0.115 12.873
clock uncertainty -0.154 12.719
SLICE_X22Y48 FDCE (Setup_fdce_C_D) -0.031 12.688 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_wdata_reg[2]
-------------------------------------------------------------------
required time 12.688
arrival time -10.641
-------------------------------------------------------------------
slack 2.047
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.049ns (arrival time - required time)
Source: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/up_he_min_reg[11]/C
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/up_xfer_data_reg[91]/D
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.391ns (logic 0.141ns (36.029%) route 0.250ns (63.971%))
Logic Levels: 0
Clock Path Skew: 0.272ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.195ns
Source Clock Delay (SCD): 0.893ns
Clock Pessimism Removal (CPR): 0.030ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.310 0.310 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4650, routed) 0.557 0.893 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/s_axi_aclk
SLICE_X44Y51 FDCE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/up_he_min_reg[11]/C
------------------------------------------------------------------- -------------------
SLICE_X44Y51 FDCE (Prop_fdce_C_Q) 0.141 1.034 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/up_he_min_reg[11]/Q
net (fo=2, routed) 0.250 1.284 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/D[75]
SLICE_X44Y44 FDCE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/up_xfer_data_reg[91]/D
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.337 0.337 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4650, routed) 0.829 1.195 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/s_axi_aclk
SLICE_X44Y44 FDCE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/up_xfer_data_reg[91]/C
clock pessimism -0.030 1.165
SLICE_X44Y44 FDCE (Hold_fdce_C_D) 0.070 1.235 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/up_xfer_data_reg[91]
-------------------------------------------------------------------
required time -1.235
arrival time 1.284
-------------------------------------------------------------------
slack 0.049
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fpga_0
Waveform(ns): { 0.000 5.000 }
Period(ns): 10.000
Sources: { i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0] }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/DCLK n/a 4.999 10.000 5.001 MMCME2_ADV_X0Y0 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/DCLK
Low Pulse Width Slow MMCME2_ADV/DCLK n/a 2.500 5.000 2.501 MMCME2_ADV_X0Y0 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/DCLK
High Pulse Width Slow MMCME2_ADV/DCLK n/a 2.500 5.000 2.500 MMCME2_ADV_X0Y0 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/DCLK
---------------------------------------------------------------------------------------------------
From Clock: clk_fpga_1
To Clock: clk_fpga_1
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 1.100ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fpga_1
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1] }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 5.000 2.845 BUFGCTRL_X0Y17 i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/I
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 5.000 95.000 MMCME2_ADV_X0Y0 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKIN1
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X0Y0 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKIN1
High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X0Y0 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: mmcm_clk_0_s
To Clock: mmcm_clk_0_s
Setup : 0 Failing Endpoints, Worst Slack 0.541ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 2.387ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.541ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[129]/C
(rising edge-triggered cell FDCE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Destination: i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[12]/R
(rising edge-triggered cell FDRE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Path Group: mmcm_clk_0_s
Path Type: Setup (Max at Slow Process Corner)
Requirement: 6.735ns (mmcm_clk_0_s rise@6.735ns - mmcm_clk_0_s rise@0.000ns)
Data Path Delay: 5.497ns (logic 2.537ns (46.154%) route 2.960ns (53.846%))
Logic Levels: 7 (CARRY4=4 LUT1=1 LUT2=1 LUT4=1)
Clock Path Skew: -0.026ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.663ns = ( 9.397 - 6.735 )
Source Clock Delay (SCD): 2.952ns
Clock Pessimism Removal (CPR): 0.263ns
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.286ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, routed) 1.193 1.193 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.101 1.294 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 1.762 3.056 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-3.715 -0.659 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, routed) 1.855 1.196 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.297 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=995, routed) 1.655 2.952 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/hdmi_clk
SLICE_X44Y50 FDCE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[129]/C
------------------------------------------------------------------- -------------------
SLICE_X44Y50 FDCE (Prop_fdce_C_Q) 0.456 3.408 f i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[129]/Q
net (fo=2, routed) 0.729 4.137 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/Q[112]
SLICE_X44Y51 LUT1 (Prop_lut1_I0_O) 0.124 4.261 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/hdmi_hs_count[0]_i_39/O
net (fo=1, routed) 0.000 4.261 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/d_data_cntrl_reg[131][1]
SLICE_X44Y51 CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 4.811 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_24/CO[3]
net (fo=1, routed) 0.000 4.811 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_24_n_0
SLICE_X44Y52 CARRY4 (Prop_carry4_CI_CO[3])
0.114 4.925 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_23/CO[3]
net (fo=1, routed) 0.000 4.925 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_23_n_0
SLICE_X44Y53 CARRY4 (Prop_carry4_CI_O[3])
0.313 5.238 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_22/O[3]
net (fo=2, routed) 0.661 5.899 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hl_width_s[11]
SLICE_X45Y53 LUT4 (Prop_lut4_I0_O) 0.306 6.205 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count[0]_i_10/O
net (fo=1, routed) 0.000 6.205 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count[0]_i_10_n_0
SLICE_X45Y53 CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 6.755 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_1/CO[3]
net (fo=33, routed) 0.930 7.685 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_1_n_0
SLICE_X45Y54 LUT2 (Prop_lut2_I1_O) 0.124 7.809 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count[0]_i_1/O
net (fo=16, routed) 0.640 8.449 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count[0]_i_1_n_0
SLICE_X46Y54 FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[12]/R
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
6.735 6.735 r
PS7_X0Y0 PS7 0.000 6.735 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, routed) 1.088 7.823 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 7.914 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 1.570 9.484 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-3.349 6.135 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, routed) 1.691 7.826 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 7.917 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=995, routed) 1.481 9.397 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
SLICE_X46Y54 FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[12]/C
clock pessimism 0.263 9.661
clock uncertainty -0.147 9.513
SLICE_X46Y54 FDRE (Setup_fdre_C_R) -0.524 8.989 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[12]
-------------------------------------------------------------------
required time 8.989
arrival time -8.449
-------------------------------------------------------------------
slack 0.541
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.055ns (arrival time - required time)
Source: i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_reg/C
(rising edge-triggered cell FDRE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Destination: i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_2d_reg_srl2/D
(rising edge-triggered cell SRL16E clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Path Group: mmcm_clk_0_s
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (mmcm_clk_0_s rise@0.000ns - mmcm_clk_0_s rise@0.000ns)
Data Path Delay: 0.437ns (logic 0.141ns (32.290%) route 0.296ns (67.710%))
Logic Levels: 0
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.191ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.030ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, routed) 0.310 0.310 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.336 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 0.580 0.915 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.122 -0.206 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, routed) 0.518 0.312 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.338 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=995, routed) 0.559 0.897 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
SLICE_X43Y51 FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_reg/C
------------------------------------------------------------------- -------------------
SLICE_X43Y51 FDRE (Prop_fdre_C_Q) 0.141 1.038 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_reg/Q
net (fo=1, routed) 0.296 1.333 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs
SLICE_X50Y46 SRL16E r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_2d_reg_srl2/D
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, routed) 0.337 0.337 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 0.366 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 0.846 1.212 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.437 -0.225 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, routed) 0.564 0.339 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.368 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=995, routed) 0.823 1.191 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
SLICE_X50Y46 SRL16E r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_2d_reg_srl2/CLK
clock pessimism -0.030 1.161
SLICE_X50Y46 SRL16E (Hold_srl16e_CLK_D)
0.117 1.278 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_2d_reg_srl2
-------------------------------------------------------------------
required time -1.278
arrival time 1.333
-------------------------------------------------------------------
slack 0.055
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: mmcm_clk_0_s
Waveform(ns): { 0.000 3.367 }
Period(ns): 6.735
Sources: { i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 6.735 4.159 RAMB36_X1Y6 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_mem/m_ram_reg/CLKARDCLK
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 6.735 206.625 MMCME2_ADV_X0Y0 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
Low Pulse Width Slow SRL16E/CLK n/a 0.980 3.367 2.387 SLICE_X50Y34 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/i_csc_1_Cr/i_add_c4/p3_ddata_reg[0]_srl6/CLK
High Pulse Width Fast SRL16E/CLK n/a 0.980 3.367 2.387 SLICE_X50Y41 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/i_csc_1_Cr/i_add_c4/p3_ddata_reg[3]_srl6/CLK
---------------------------------------------------------------------------------------------------
From Clock: mmcm_fb_clk_s
To Clock: mmcm_fb_clk_s
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 45.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: mmcm_fb_clk_s
Waveform(ns): { 0.000 27.500 }
Period(ns): 55.000
Sources: { i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 55.000 52.845 BUFGCTRL_X0Y2 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_fb_clk_bufg/I
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 55.000 45.000 MMCME2_ADV_X0Y0 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
To Clock: i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 1.100ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 5.000 3.751 MMCME2_ADV_X1Y0 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKIN1
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 5.000 95.000 MMCME2_ADV_X1Y0 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKIN1
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y0 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKIN1
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y0 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: clk_out1_system_sys_audio_clkgen_0
To Clock: clk_out1_system_sys_audio_clkgen_0
Setup : 0 Failing Endpoints, Worst Slack 78.403ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.037ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 39.440ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 78.403ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/rd_addr_reg[1]/C
(rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Destination: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]/D
(rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Path Group: clk_out1_system_sys_audio_clkgen_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 81.380ns (clk_out1_system_sys_audio_clkgen_0 rise@81.380ns - clk_out1_system_sys_audio_clkgen_0 rise@0.000ns)
Data Path Delay: 2.488ns (logic 0.795ns (31.954%) route 1.693ns (68.046%))
Logic Levels: 1 (RAMD32=1)
Clock Path Skew: -0.023ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.512ns = ( 82.892 - 81.380 )
Source Clock Delay (SCD): 1.684ns
Clock Pessimism Removal (CPR): 0.149ns
Clock Uncertainty: 0.168ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.328ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_system_sys_audio_clkgen_0 rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 1.806 1.806 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-3.793 -1.987 r i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.889 -0.098 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 0.003 r i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
net (fo=36, routed) 1.681 1.684 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/DATA_CLK_I
SLICE_X26Y72 FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/rd_addr_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X26Y72 FDRE (Prop_fdre_C_Q) 0.478 2.162 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/rd_addr_reg[1]/Q
net (fo=7, routed) 1.132 3.294 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/ADDRA1
SLICE_X26Y73 RAMD32 (Prop_ramd32_RADR1_O)
0.317 3.611 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMA/O
net (fo=1, routed) 0.561 4.172 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data0[0]
SLICE_X27Y73 FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_system_sys_audio_clkgen_0 rise edge)
81.380 81.380 r
BUFGCTRL_X0Y17 BUFG 0.000 81.380 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 1.612 82.993 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-3.425 79.567 r i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.725 81.292 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 81.383 r i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
net (fo=36, routed) 1.509 82.892 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/DATA_CLK_I
SLICE_X27Y73 FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]/C
clock pessimism 0.149 83.041
clock uncertainty -0.168 82.874
SLICE_X27Y73 FDRE (Setup_fdre_C_D) -0.299 82.575 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]
-------------------------------------------------------------------
required time 82.575
arrival time -4.172
-------------------------------------------------------------------
slack 78.403
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.037ns (arrival time - required time)
Source: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_sync_fifo_in_reg[0]/C
(rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Destination: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/I
(rising edge-triggered cell RAMD32 clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Path Group: clk_out1_system_sys_audio_clkgen_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_system_sys_audio_clkgen_0 rise@0.000ns - clk_out1_system_sys_audio_clkgen_0 rise@0.000ns)
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
Logic Levels: 0
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.836ns
Source Clock Delay (SCD): 0.568ns
Clock Pessimism Removal (CPR): 0.255ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_system_sys_audio_clkgen_0 rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 0.597 0.597 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.149 -0.553 r i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.529 -0.024 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.002 r i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
net (fo=36, routed) 0.566 0.568 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/DATA_CLK_I
SLICE_X27Y70 FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_sync_fifo_in_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X27Y70 FDRE (Prop_fdre_C_Q) 0.141 0.709 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_sync_fifo_in_reg[0]/Q
net (fo=1, routed) 0.056 0.765 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/DIA0
SLICE_X26Y70 RAMD32 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/I
------------------------------------------------------------------- -------------------
(clock clk_out1_system_sys_audio_clkgen_0 rise edge)
0.000 0.000 r
BUFGCTRL_X0Y17 BUFG 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 0.864 0.864 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.467 -0.603 r i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.576 -0.027 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 0.002 r i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
net (fo=36, routed) 0.834 0.836 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/WCLK
SLICE_X26Y70 RAMD32 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
clock pessimism -0.255 0.581
SLICE_X26Y70 RAMD32 (Hold_ramd32_CLK_I)
0.147 0.728 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA
-------------------------------------------------------------------
required time -0.728
arrival time 0.765
-------------------------------------------------------------------
slack 0.037
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_out1_system_sys_audio_clkgen_0
Waveform(ns): { 0.000 40.690 }
Period(ns): 81.380
Sources: { i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 81.380 79.225 BUFGCTRL_X0Y1 i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/I
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 81.380 131.980 MMCME2_ADV_X1Y0 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
Low Pulse Width Fast RAMD32/CLK n/a 1.250 40.690 39.440 SLICE_X26Y70 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.250 40.690 39.440 SLICE_X26Y70 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: clkfbout_system_sys_audio_clkgen_0
To Clock: clkfbout_system_sys_audio_clkgen_0
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 42.845ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clkfbout_system_sys_audio_clkgen_0
Waveform(ns): { 0.000 22.500 }
Period(ns): 45.000
Sources: { i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 45.000 42.845 BUFGCTRL_X0Y3 i_system_wrapper/system_i/sys_audio_clkgen/inst/clkf_buf/I
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 45.000 55.000 MMCME2_ADV_X1Y0 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: clk_out1_system_sys_audio_clkgen_0
To Clock: clk_fpga_0
Setup : 0 Failing Endpoints, Worst Slack 7.881ns, Total Violation 0.000ns
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 7.881ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMB/CLK
(rising edge-triggered cell RAMD32 clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Destination: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/out_data_reg[2]/D
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (MaxDelay Path 10.000ns)
Data Path Delay: 1.867ns (logic 1.343ns (71.923%) route 0.524ns (28.077%))
Logic Levels: 0
Timing Exception: MaxDelay Path 10.000ns -datapath_only
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
SLICE_X26Y70 0.000 0.000 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMB/CLK
SLICE_X26Y70 RAMD32 (Prop_ramd32_CLK_O)
1.343 1.343 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMB/O
net (fo=1, routed) 0.524 1.867 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/out_data0__0[2]
SLICE_X26Y71 FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/out_data_reg[2]/D
------------------------------------------------------------------- -------------------
max delay 10.000 10.000
SLICE_X26Y71 FDRE (Setup_fdre_C_D) -0.252 9.748 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/out_data_reg[2]
-------------------------------------------------------------------
required time 9.748
arrival time -1.867
-------------------------------------------------------------------
slack 7.881
---------------------------------------------------------------------------------------------------
From Clock: clk_fpga_0
To Clock: clk_out1_system_sys_audio_clkgen_0
Setup : 0 Failing Endpoints, Worst Slack 79.176ns, Total Violation 0.000ns
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 79.176ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMA/CLK
(rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]/D
(rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Path Group: clk_out1_system_sys_audio_clkgen_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 81.380ns (MaxDelay Path 81.380ns)
Data Path Delay: 1.905ns (logic 1.344ns (70.553%) route 0.561ns (29.447%))
Logic Levels: 0
Timing Exception: MaxDelay Path 81.380ns -datapath_only
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
SLICE_X26Y73 0.000 0.000 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMA/CLK
SLICE_X26Y73 RAMD32 (Prop_ramd32_CLK_O)
1.344 1.344 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMA/O
net (fo=1, routed) 0.561 1.905 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data0[0]
SLICE_X27Y73 FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]/D
------------------------------------------------------------------- -------------------
max delay 81.380 81.380
SLICE_X27Y73 FDRE (Setup_fdre_C_D) -0.299 81.081 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]
-------------------------------------------------------------------
required time 81.081
arrival time -1.905
-------------------------------------------------------------------
slack 79.176
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: clk_fpga_0
To Clock: clk_fpga_0
Setup : 0 Failing Endpoints, Worst Slack 2.596ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.334ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.596ns (required time - arrival time)
Source: i_system_wrapper/system_i/sys_rstgen/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_wreq_reg/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 6.680ns (logic 0.580ns (8.682%) route 6.100ns (91.318%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.164ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.641ns = ( 12.641 - 10.000 )
Source Clock Delay (SCD): 2.934ns
Clock Pessimism Removal (CPR): 0.129ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.193 1.193 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4650, routed) 1.640 2.934 i_system_wrapper/system_i/sys_rstgen/U0/slowest_sync_clk
SLICE_X53Y97 FDRE r i_system_wrapper/system_i/sys_rstgen/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X53Y97 FDRE (Prop_fdre_C_Q) 0.456 3.390 r i_system_wrapper/system_i/sys_rstgen/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
net (fo=81, routed) 3.651 7.041 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/s_axi_aresetn
SLICE_X16Y37 LUT1 (Prop_lut1_I0_O) 0.124 7.165 f i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_raddr[7]_i_1/O
net (fo=107, routed) 2.450 9.614 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_wreq_reg_0
SLICE_X33Y74 FDCE f i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_wreq_reg/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.088 11.088 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.179 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4650, routed) 1.462 12.641 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/s_axi_aclk
SLICE_X33Y74 FDCE r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_wreq_reg/C
clock pessimism 0.129 12.770
clock uncertainty -0.154 12.616
SLICE_X33Y74 FDCE (Recov_fdce_C_CLR) -0.405 12.211 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_axi/up_wreq_reg
-------------------------------------------------------------------
required time 12.211
arrival time -9.614
-------------------------------------------------------------------
slack 2.596
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.334ns (arrival time - required time)
Source: i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
(rising edge-triggered cell FDPE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.258ns (logic 0.141ns (54.719%) route 0.117ns (45.281%))
Logic Levels: 0
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.230ns
Source Clock Delay (SCD): 0.931ns
Clock Pessimism Removal (CPR): 0.284ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.310 0.310 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4650, routed) 0.595 0.930 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
SLICE_X15Y42 FDPE r i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X15Y42 FDPE (Prop_fdpe_C_Q) 0.141 1.071 f i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
net (fo=15, routed) 0.117 1.188 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Q[0]
SLICE_X13Y42 FDCE f i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.337 0.337 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4650, routed) 0.864 1.230 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
SLICE_X13Y42 FDCE r i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/C
clock pessimism -0.284 0.947
SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 0.854 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]
-------------------------------------------------------------------
required time -0.854
arrival time 1.188
-------------------------------------------------------------------
slack 0.334
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: mmcm_clk_0_s
To Clock: mmcm_clk_0_s
Setup : 0 Failing Endpoints, Worst Slack 2.115ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.290ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.115ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
(rising edge-triggered cell FDRE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Destination: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[100]/CLR
(recovery check against rising-edge clock mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 6.735ns (mmcm_clk_0_s rise@6.735ns - mmcm_clk_0_s rise@0.000ns)
Data Path Delay: 3.889ns (logic 0.518ns (13.320%) route 3.371ns (86.680%))
Logic Levels: 0
Clock Path Skew: -0.178ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.665ns = ( 9.399 - 6.735 )
Source Clock Delay (SCD): 2.958ns
Clock Pessimism Removal (CPR): 0.115ns
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.286ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, routed) 1.193 1.193 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.101 1.294 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 1.762 3.056 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-3.715 -0.659 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, routed) 1.855 1.196 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.297 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=995, routed) 1.661 2.958 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/hdmi_clk
SLICE_X46Y37 FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
------------------------------------------------------------------- -------------------
SLICE_X46Y37 FDRE (Prop_fdre_C_Q) 0.518 3.476 f i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/Q
net (fo=193, routed) 3.371 6.847 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/rst_reg
SLICE_X40Y52 FDCE f i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[100]/CLR
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
6.735 6.735 r
PS7_X0Y0 PS7 0.000 6.735 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, routed) 1.088 7.823 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 7.914 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 1.570 9.484 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-3.349 6.135 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, routed) 1.691 7.826 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 7.917 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=995, routed) 1.483 9.399 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/hdmi_clk
SLICE_X40Y52 FDCE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[100]/C
clock pessimism 0.115 9.514
clock uncertainty -0.147 9.367
SLICE_X40Y52 FDCE (Recov_fdce_C_CLR) -0.405 8.962 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[100]
-------------------------------------------------------------------
required time 8.962
arrival time -6.847
-------------------------------------------------------------------
slack 2.115
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.290ns (arrival time - required time)
Source: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
(rising edge-triggered cell FDRE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Destination: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_xfer_toggle_m2_reg/CLR
(removal check against rising-edge clock mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (mmcm_clk_0_s rise@0.000ns - mmcm_clk_0_s rise@0.000ns)
Data Path Delay: 0.454ns (logic 0.164ns (36.131%) route 0.290ns (63.869%))
Logic Levels: 0
Clock Path Skew: 0.256ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.186ns
Source Clock Delay (SCD): 0.895ns
Clock Pessimism Removal (CPR): 0.035ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, routed) 0.310 0.310 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.336 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 0.580 0.915 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.122 -0.206 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, routed) 0.518 0.312 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.338 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=995, routed) 0.557 0.894 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/hdmi_clk
SLICE_X46Y37 FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
------------------------------------------------------------------- -------------------
SLICE_X46Y37 FDRE (Prop_fdre_C_Q) 0.164 1.058 f i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/Q
net (fo=193, routed) 0.290 1.348 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/rst_reg
SLICE_X51Y36 FDCE f i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_xfer_toggle_m2_reg/CLR
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, routed) 0.337 0.337 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 0.366 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, routed) 0.846 1.212 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.437 -0.225 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, routed) 0.564 0.339 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.368 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=995, routed) 0.818 1.186 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/hdmi_clk
SLICE_X51Y36 FDCE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_xfer_toggle_m2_reg/C
clock pessimism -0.035 1.151
SLICE_X51Y36 FDCE (Remov_fdce_C_CLR) -0.092 1.059 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_xfer_toggle_m2_reg
-------------------------------------------------------------------
required time -1.059
arrival time 1.348
-------------------------------------------------------------------
slack 0.290
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