Слияние кода завершено, страница обновится автоматически
Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
| Date : Wed Dec 02 15:08:25 2015
| Host : FS running 64-bit Service Pack 1 (build 7601)
| Command : report_timing_summary -file timing_synth.log
| Design : system_top
| Device : 7z020-clg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 7 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 30 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.226 0.000 0 13640 -0.151 -9.658 64 13640 1.100 0.000 0 5872
Timing constraints are not met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk_fpga_0 {0.000 5.000} 10.000 100.000
clk_fpga_1 {0.000 2.500} 5.000 200.000
mmcm_clk_0_s {0.000 3.367} 6.735 148.485
mmcm_clk_1_s {0.000 3.367} 6.735 148.485
mmcm_fb_clk_s {0.000 27.500} 55.000 18.182
i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1 {0.000 2.500} 5.000 200.000
clk_out1_system_sys_audio_clkgen_0 {0.000 40.690} 81.380 12.288
clkfbout_system_sys_audio_clkgen_0 {0.000 22.500} 45.000 22.222
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk_fpga_0 3.407 0.000 0 10891 -0.151 -9.658 64 10891 2.500 0.000 0 4739
clk_fpga_1 1.100 0.000 0 2
mmcm_clk_0_s 0.226 0.000 0 1453 0.195 0.000 0 1453 2.387 0.000 0 1085
mmcm_clk_1_s 4.579 0.000 0 2
mmcm_fb_clk_s 45.000 0.000 0 3
i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1 1.100 0.000 0 1
clk_out1_system_sys_audio_clkgen_0 78.985 0.000 0 61 0.173 0.000 0 61 39.440 0.000 0 37
clkfbout_system_sys_audio_clkgen_0 42.845 0.000 0 3
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
clk_out1_system_sys_audio_clkgen_0 clk_fpga_0 8.273 0.000 0 4
clk_fpga_0 clk_out1_system_sys_audio_clkgen_0 79.653 0.000 0 5
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** clk_fpga_0 clk_fpga_0 7.344 0.000 0 1054 0.419 0.000 0 1054
**async_default** mmcm_clk_0_s mmcm_clk_0_s 5.086 0.000 0 181 0.464 0.000 0 181
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: clk_fpga_0
To Clock: clk_fpga_0
Setup : 0 Failing Endpoints, Worst Slack 3.407ns, Total Violation 0.000ns
Hold : 64 Failing Endpoints, Worst Slack -0.151ns, Total Violation -9.658ns
PW : 0 Failing Endpoints, Worst Slack 2.500ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 3.407ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_iic_main/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/sys_ps7/inst/PS7_i/MAXIGP0WREADY
(rising edge-triggered cell PS7 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 4.756ns (logic 1.560ns (32.802%) route 3.196ns (67.198%))
Logic Levels: 5 (LUT4=2 LUT5=1 LUT6=1 MUXF7=1)
Clock Path Skew: -0.800ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.091ns = ( 10.091 - 10.000 )
Source Clock Delay (SCD): 0.901ns
Clock Pessimism Removal (CPR): 0.010ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFG (Prop_bufg_I_O) 0.101 0.101 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4752, unplaced) 0.800 0.901 i_system_wrapper/system_i/axi_iic_main/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_aclk
FDRE r i_system_wrapper/system_i/axi_iic_main/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 1.379 f i_system_wrapper/system_i/axi_iic_main/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]/Q
net (fo=5, unplaced) 0.769 2.148 i_system_wrapper/system_i/axi_iic_main/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3][0]
LUT4 (Prop_lut4_I1_O) 0.295 2.443 f i_system_wrapper/system_i/axi_iic_main/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0_i_1/O
net (fo=2, unplaced) 0.676 3.119 i_system_wrapper/system_i/axi_iic_main/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0_i_1_n_0
LUT4 (Prop_lut4_I0_O) 0.124 3.243 r i_system_wrapper/system_i/axi_iic_main/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/O
net (fo=6, unplaced) 0.481 3.724 i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/splitter_aw/m_axi_wready[0]
LUT6 (Prop_lut6_I5_O) 0.124 3.848 r i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/splitter_aw/s_axi_wready[0]_INST_0_i_2/O
net (fo=3, unplaced) 0.000 3.848 i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/gen_decerr.decerr_slave_inst/GEN_LITE_IS_SYNC.wready_out_i_reg
MUXF7 (Prop_muxf7_I0_O) 0.241 4.089 r i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/gen_decerr.decerr_slave_inst/s_axi_wready[0]_INST_0_i_1/O
net (fo=3, unplaced) 0.470 4.559 i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/m_atarget_enc_reg[0]_0
LUT5 (Prop_lut5_I0_O) 0.298 4.857 r i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_axi_wready[0]_INST_0/O
net (fo=1, unplaced) 0.800 5.657 i_system_wrapper/system_i/sys_ps7/inst/M_AXI_GP0_WREADY
PS7_X0Y0 PS7 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/MAXIGP0WREADY
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, unplaced) 0.000 10.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFG (Prop_bufg_I_O) 0.091 10.091 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4752, unplaced) 0.000 10.091 i_system_wrapper/system_i/sys_ps7/inst/M_AXI_GP0_ACLK
PS7_X0Y0 PS7 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/MAXIGP0ACLK
clock pessimism 0.010 10.101
clock uncertainty -0.154 9.947
PS7_X0Y0 PS7 (Setup_ps7_MAXIGP0ACLK_MAXIGP0WREADY)
-0.883 9.064 i_system_wrapper/system_i/sys_ps7/inst/PS7_i
-------------------------------------------------------------------
required time 9.064
arrival time -5.657
-------------------------------------------------------------------
slack 3.407
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -0.151ns (arrival time - required time)
Source: i_system_wrapper/system_i/sys_ps7/inst/PS7_i/SAXIHP0ACLK
(rising edge-triggered cell PS7 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/axi_hdmi_dma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/fg_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIADI[0]
(rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.359ns (logic 0.359ns (100.000%) route 0.000ns (0.000%))
Logic Levels: 0
Clock Path Skew: 0.355ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.384ns
Source Clock Delay (SCD): 0.026ns
Clock Pessimism Removal (CPR): 0.003ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFG (Prop_bufg_I_O) 0.026 0.026 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4752, unplaced) 0.000 0.026 i_system_wrapper/system_i/sys_ps7/inst/S_AXI_HP0_ACLK
PS7_X0Y0 PS7 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/SAXIHP0ACLK
------------------------------------------------------------------- -------------------
PS7_X0Y0 PS7 (Prop_ps7_SAXIHP0ACLK_SAXIHP0RDATA[0])
0.359 0.385 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/SAXIHP0RDATA[0]
net (fo=1, unplaced) 0.000 0.385 i_system_wrapper/system_i/axi_hdmi_dma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/fg_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/m_axi_mm2s_rdata[0]
RAMB36E1 r i_system_wrapper/system_i/axi_hdmi_dma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/fg_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIADI[0]
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFG (Prop_bufg_I_O) 0.029 0.029 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4752, unplaced) 0.355 0.384 i_system_wrapper/system_i/axi_hdmi_dma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/fg_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/m_axi_mm2s_aclk
RAMB36E1 r i_system_wrapper/system_i/axi_hdmi_dma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/fg_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/CLKBWRCLK
clock pessimism -0.003 0.381
RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIADI[0])
0.155 0.536 i_system_wrapper/system_i/axi_hdmi_dma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/fg_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram
-------------------------------------------------------------------
required time -0.536
arrival time 0.385
-------------------------------------------------------------------
slack -0.151
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fpga_0
Waveform(ns): { 0.000 5.000 }
Period(ns): 10.000
Sources: { i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0] }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/DCLK n/a 4.999 10.000 5.001 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/DCLK
Low Pulse Width Slow MMCME2_ADV/DCLK n/a 2.500 5.000 2.500 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/DCLK
High Pulse Width Slow MMCME2_ADV/DCLK n/a 2.500 5.000 2.500 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/DCLK
---------------------------------------------------------------------------------------------------
From Clock: clk_fpga_1
To Clock: clk_fpga_1
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 1.100ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fpga_1
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1] }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 5.000 2.845 i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/I
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 5.000 95.000 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKIN1
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKIN1
High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: mmcm_clk_0_s
To Clock: mmcm_clk_0_s
Setup : 0 Failing Endpoints, Worst Slack 0.226ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.195ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 2.387ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.226ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[131]/C
(rising edge-triggered cell FDCE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Destination: i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[0]/R
(rising edge-triggered cell FDRE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Path Group: mmcm_clk_0_s
Path Type: Setup (Max at Slow Process Corner)
Requirement: 6.735ns (mmcm_clk_0_s rise@6.735ns - mmcm_clk_0_s rise@0.000ns)
Data Path Delay: 5.764ns (logic 2.457ns (42.627%) route 3.307ns (57.373%))
Logic Levels: 6 (CARRY4=4 LUT2=1 LUT4=1)
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.851ns = ( 7.586 - 6.735 )
Source Clock Delay (SCD): 0.901ns
Clock Pessimism Removal (CPR): 0.010ns
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.286ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFG (Prop_bufg_I_O) 0.101 0.101 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.800 0.901 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.701 -0.800 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, unplaced) 0.800 0.000 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFG (Prop_bufg_I_O) 0.101 0.101 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=1083, unplaced) 0.800 0.901 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/hdmi_clk
FDCE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[131]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 1.379 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_reg[131]/Q
net (fo=2, unplaced) 0.658 2.037 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/d_data_cntrl_reg[188][114]
CARRY4 (Prop_carry4_DI[3]_CO[3])
0.567 2.604 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_24/CO[3]
net (fo=1, unplaced) 0.009 2.613 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_24_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.117 2.730 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_23/CO[3]
net (fo=1, unplaced) 0.000 2.730 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_23_n_0
CARRY4 (Prop_carry4_CI_O[3])
0.331 3.061 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_22/O[3]
net (fo=2, unplaced) 0.819 3.880 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hl_width_s[11]
LUT4 (Prop_lut4_I0_O) 0.307 4.187 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count[0]_i_10/O
net (fo=1, unplaced) 0.000 4.187 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count[0]_i_10_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.533 4.720 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_1/CO[3]
net (fo=33, unplaced) 0.990 5.710 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count_reg[0]_i_1_n_0
LUT2 (Prop_lut2_I1_O) 0.124 5.834 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count[0]_i_1/O
net (fo=16, unplaced) 0.831 6.665 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count[0]_i_1_n_0
FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[0]/R
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
6.735 6.735 r
PS7_X0Y0 PS7 0.000 6.735 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, unplaced) 0.000 6.735 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFG (Prop_bufg_I_O) 0.091 6.826 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.760 7.586 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.611 5.975 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, unplaced) 0.760 6.735 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFG (Prop_bufg_I_O) 0.091 6.826 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=1083, unplaced) 0.760 7.586 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[0]/C
clock pessimism 0.010 7.596
clock uncertainty -0.147 7.448
FDRE (Setup_fdre_C_R) -0.557 6.891 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[0]
-------------------------------------------------------------------
required time 6.891
arrival time -6.665
-------------------------------------------------------------------
slack 0.226
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.195ns (arrival time - required time)
Source: i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vsync_data_e_reg/C
(rising edge-triggered cell FDRE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Destination: i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/i_csc_1_Cr/i_add_c4/p3_ddata_reg[1]_srl6/D
(rising edge-triggered cell SRL16E clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Path Group: mmcm_clk_0_s
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (mmcm_clk_0_s rise@0.000ns - mmcm_clk_0_s rise@0.000ns)
Data Path Delay: 0.277ns (logic 0.131ns (47.319%) route 0.146ns (52.681%))
Logic Levels: 0
Clock Path Skew: 0.018ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.384ns
Source Clock Delay (SCD): 0.363ns
Clock Pessimism Removal (CPR): 0.003ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFG (Prop_bufg_I_O) 0.026 0.026 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.337 0.363 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-0.700 -0.337 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, unplaced) 0.337 -0.000 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFG (Prop_bufg_I_O) 0.026 0.026 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=1083, unplaced) 0.337 0.363 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vsync_data_e_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.131 0.494 r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vsync_data_e_reg/Q
net (fo=2, unplaced) 0.146 0.640 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/i_csc_1_Cr/i_add_c4/hdmi_vsync_data_e
SRL16E r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/i_csc_1_Cr/i_add_c4/p3_ddata_reg[1]_srl6/D
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFG (Prop_bufg_I_O) 0.029 0.029 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.355 0.384 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-0.739 -0.355 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, unplaced) 0.355 0.000 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFG (Prop_bufg_I_O) 0.029 0.029 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=1083, unplaced) 0.355 0.384 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/i_csc_1_Cr/i_add_c4/hdmi_clk
SRL16E r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/i_csc_1_Cr/i_add_c4/p3_ddata_reg[1]_srl6/CLK
clock pessimism -0.003 0.381
SRL16E (Hold_srl16e_CLK_D)
0.064 0.445 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/i_csc_1_Cr/i_add_c4/p3_ddata_reg[1]_srl6
-------------------------------------------------------------------
required time -0.445
arrival time 0.640
-------------------------------------------------------------------
slack 0.195
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: mmcm_clk_0_s
Waveform(ns): { 0.000 3.367 }
Period(ns): 6.735
Sources: { i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 6.735 4.159 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_mem/m_ram_reg/CLKARDCLK
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 6.735 206.625 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
Low Pulse Width Slow SRL16E/CLK n/a 0.980 3.367 2.387 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_2d_reg_srl2/CLK
High Pulse Width Slow SRL16E/CLK n/a 0.980 3.367 2.387 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_2d_reg_srl2/CLK
---------------------------------------------------------------------------------------------------
From Clock: mmcm_clk_1_s
To Clock: mmcm_clk_1_s
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 4.579ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: mmcm_clk_1_s
Waveform(ns): { 0.000 3.367 }
Period(ns): 6.735
Sources: { i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 6.735 4.579 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_1_bufg/I
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 6.735 206.625 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT1
---------------------------------------------------------------------------------------------------
From Clock: mmcm_fb_clk_s
To Clock: mmcm_fb_clk_s
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 45.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: mmcm_fb_clk_s
Waveform(ns): { 0.000 27.500 }
Period(ns): 55.000
Sources: { i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 55.000 52.845 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_fb_clk_bufg/I
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 55.000 45.000 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
To Clock: i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 1.100ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 5.000 3.751 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKIN1
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 5.000 95.000 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKIN1
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKIN1
High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: clk_out1_system_sys_audio_clkgen_0
To Clock: clk_out1_system_sys_audio_clkgen_0
Setup : 0 Failing Endpoints, Worst Slack 78.985ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.173ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 39.440ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 78.985ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/rd_addr_reg[0]/C
(rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Destination: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[4]/D
(rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Path Group: clk_out1_system_sys_audio_clkgen_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 81.380ns (clk_out1_system_sys_audio_clkgen_0 rise@81.380ns - clk_out1_system_sys_audio_clkgen_0 rise@0.000ns)
Data Path Delay: 2.139ns (logic 0.802ns (37.494%) route 1.337ns (62.506%))
Logic Levels: 1 (RAMD32=1)
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.760ns = ( 82.140 - 81.380 )
Source Clock Delay (SCD): 0.800ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.168ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.328ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_system_sys_audio_clkgen_0 rise edge)
0.000 0.000 r
BUFG 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.800 0.800 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.701 -0.901 r i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.800 -0.101 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
BUFG (Prop_bufg_I_O) 0.101 0.000 r i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
net (fo=36, unplaced) 0.800 0.800 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/DATA_CLK_I
FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/rd_addr_reg[0]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 1.278 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/rd_addr_reg[0]/Q
net (fo=8, unplaced) 1.003 2.281 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/ADDRC0
RAMD32 (Prop_ramd32_RADR0_O)
0.324 2.605 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMC/O
net (fo=1, unplaced) 0.334 2.939 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data0[4]
FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[4]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_system_sys_audio_clkgen_0 rise edge)
81.380 81.380 r
BUFG 0.000 81.380 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.760 82.140 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.611 80.529 r i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.760 81.289 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
BUFG (Prop_bufg_I_O) 0.091 81.380 r i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
net (fo=36, unplaced) 0.760 82.140 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/DATA_CLK_I
FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[4]/C
clock pessimism 0.000 82.140
clock uncertainty -0.168 81.972
FDRE (Setup_fdre_C_D) -0.049 81.923 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[4]
-------------------------------------------------------------------
required time 81.923
arrival time -2.939
-------------------------------------------------------------------
slack 78.985
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.173ns (arrival time - required time)
Source: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/cdc_sync_stage1_tick_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Destination: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/cdc_sync_stage2_tick_reg/D
(rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Path Group: clk_out1_system_sys_audio_clkgen_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_system_sys_audio_clkgen_0 rise@0.000ns - clk_out1_system_sys_audio_clkgen_0 rise@0.000ns)
Data Path Delay: 0.228ns (logic 0.147ns (64.374%) route 0.081ns (35.626%))
Logic Levels: 0
Clock Path Skew: 0.018ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.355ns
Source Clock Delay (SCD): 0.337ns
Clock Pessimism Removal (CPR): -0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_system_sys_audio_clkgen_0 rise edge)
0.000 0.000 r
BUFG 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.337 0.337 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-0.700 -0.363 r i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.337 -0.026 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
BUFG (Prop_bufg_I_O) 0.026 -0.000 r i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
net (fo=36, unplaced) 0.337 0.337 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/DATA_CLK_I
FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/cdc_sync_stage1_tick_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.147 0.484 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/cdc_sync_stage1_tick_reg/Q
net (fo=1, unplaced) 0.081 0.566 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/cdc_sync_stage1_tick
FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/cdc_sync_stage2_tick_reg/D
------------------------------------------------------------------- -------------------
(clock clk_out1_system_sys_audio_clkgen_0 rise edge)
0.000 0.000 r
BUFG 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.355 0.355 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-0.739 -0.384 r i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.355 -0.029 i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
BUFG (Prop_bufg_I_O) 0.029 0.000 r i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
net (fo=36, unplaced) 0.355 0.355 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/DATA_CLK_I
FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/cdc_sync_stage2_tick_reg/C
clock pessimism 0.000 0.355
FDRE (Hold_fdre_C_D) 0.038 0.393 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/cdc_sync_stage2_tick_reg
-------------------------------------------------------------------
required time -0.393
arrival time 0.566
-------------------------------------------------------------------
slack 0.173
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_out1_system_sys_audio_clkgen_0
Waveform(ns): { 0.000 40.690 }
Period(ns): 81.380
Sources: { i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 81.380 79.225 i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/I
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 81.380 131.980 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
Low Pulse Width Slow RAMD32/CLK n/a 1.250 40.690 39.440 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.250 40.690 39.440 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: clkfbout_system_sys_audio_clkgen_0
To Clock: clkfbout_system_sys_audio_clkgen_0
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 42.845ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clkfbout_system_sys_audio_clkgen_0
Waveform(ns): { 0.000 22.500 }
Period(ns): 45.000
Sources: { i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 45.000 42.845 i_system_wrapper/system_i/sys_audio_clkgen/inst/clkf_buf/I
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 45.000 55.000 i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: clk_out1_system_sys_audio_clkgen_0
To Clock: clk_fpga_0
Setup : 0 Failing Endpoints, Worst Slack 8.273ns, Total Violation 0.000ns
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 8.273ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
(rising edge-triggered cell RAMD32 clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Destination: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/out_data_reg[0]/D
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (MaxDelay Path 10.000ns)
Data Path Delay: 1.678ns (logic 1.344ns (80.095%) route 0.334ns (19.905%))
Logic Levels: 0
Timing Exception: MaxDelay Path 10.000ns -datapath_only
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
0.000 0.000 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
RAMD32 (Prop_ramd32_CLK_O)
1.344 1.344 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/O
net (fo=1, unplaced) 0.334 1.678 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/out_data0__0[0]
FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/out_data_reg[0]/D
------------------------------------------------------------------- -------------------
max delay 10.000 10.000
FDRE (Setup_fdre_C_D) -0.049 9.951 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/rx_gen.rx_sync/out_data_reg[0]
-------------------------------------------------------------------
required time 9.951
arrival time -1.678
-------------------------------------------------------------------
slack 8.273
---------------------------------------------------------------------------------------------------
From Clock: clk_fpga_0
To Clock: clk_out1_system_sys_audio_clkgen_0
Setup : 0 Failing Endpoints, Worst Slack 79.653ns, Total Violation 0.000ns
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 79.653ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMA/CLK
(rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]/D
(rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0 {rise@0.000ns fall@40.690ns period=81.380ns})
Path Group: clk_out1_system_sys_audio_clkgen_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 81.380ns (MaxDelay Path 81.380ns)
Data Path Delay: 1.678ns (logic 1.344ns (80.095%) route 0.334ns (19.905%))
Logic Levels: 0
Timing Exception: MaxDelay Path 81.380ns -datapath_only
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
0.000 0.000 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMA/CLK
RAMD32 (Prop_ramd32_CLK_O)
1.344 1.344 r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMA/O
net (fo=1, unplaced) 0.334 1.678 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data0[0]
FDRE r i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]/D
------------------------------------------------------------------- -------------------
max delay 81.380 81.380
FDRE (Setup_fdre_C_D) -0.049 81.331 i_system_wrapper/system_i/axi_i2s_adi/inst/ctrl/tx_sync/out_data_reg[0]
-------------------------------------------------------------------
required time 81.331
arrival time -1.678
-------------------------------------------------------------------
slack 79.653
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: clk_fpga_0
To Clock: clk_fpga_0
Setup : 0 Failing Endpoints, Worst Slack 7.344ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.419ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 7.344ns (required time - arrival time)
Source: i_system_wrapper/system_i/sys_rstgen/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 2.068ns (logic 0.773ns (37.379%) route 1.295ns (62.621%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.851ns = ( 10.851 - 10.000 )
Source Clock Delay (SCD): 0.901ns
Clock Pessimism Removal (CPR): 0.010ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFG (Prop_bufg_I_O) 0.101 0.101 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4752, unplaced) 0.800 0.901 i_system_wrapper/system_i/sys_rstgen/U0/slowest_sync_clk
FDRE r i_system_wrapper/system_i/sys_rstgen/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 1.379 r i_system_wrapper/system_i/sys_rstgen/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
net (fo=90, unplaced) 0.408 1.787 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/aresetn
LUT1 (Prop_lut1_I0_O) 0.295 2.082 f i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/S_AXI_ASIZE_Q[2]_i_1/O
net (fo=149, unplaced) 0.887 2.969 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
FDPE f i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, unplaced) 0.000 10.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFG (Prop_bufg_I_O) 0.091 10.091 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4752, unplaced) 0.760 10.851 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
FDPE r i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/C
clock pessimism 0.010 10.861
clock uncertainty -0.154 10.707
FDPE (Recov_fdpe_C_PRE) -0.394 10.313 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
-------------------------------------------------------------------
required time 10.313
arrival time -2.969
-------------------------------------------------------------------
slack 7.344
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.419ns (arrival time - required time)
Source: i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C
(rising edge-triggered cell FDPE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.292ns (logic 0.147ns (50.342%) route 0.145ns (49.658%))
Logic Levels: 0
Clock Path Skew: 0.018ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.384ns
Source Clock Delay (SCD): 0.363ns
Clock Pessimism Removal (CPR): 0.003ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFG (Prop_bufg_I_O) 0.026 0.026 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4752, unplaced) 0.337 0.363 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
FDPE r i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.147 0.510 f i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/Q
net (fo=1, unplaced) 0.145 0.655 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_rd_reg2
FDPE f i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
BUFG (Prop_bufg_I_O) 0.029 0.029 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4752, unplaced) 0.355 0.384 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
FDPE r i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/C
clock pessimism -0.003 0.381
FDPE (Remov_fdpe_C_PRE) -0.145 0.236 i_system_wrapper/system_i/axi_hp0_interconnect/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
-------------------------------------------------------------------
required time -0.236
arrival time 0.655
-------------------------------------------------------------------
slack 0.419
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: mmcm_clk_0_s
To Clock: mmcm_clk_0_s
Setup : 0 Failing Endpoints, Worst Slack 5.086ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.464ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 5.086ns (required time - arrival time)
Source: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
(rising edge-triggered cell FDRE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Destination: i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/CLR
(recovery check against rising-edge clock mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 6.735ns (mmcm_clk_0_s rise@6.735ns - mmcm_clk_0_s rise@0.000ns)
Data Path Delay: 0.938ns (logic 0.478ns (50.959%) route 0.460ns (49.041%))
Logic Levels: 0
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.851ns = ( 7.586 - 6.735 )
Source Clock Delay (SCD): 0.901ns
Clock Pessimism Removal (CPR): 0.010ns
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.286ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFG (Prop_bufg_I_O) 0.101 0.101 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.800 0.901 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.701 -0.800 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, unplaced) 0.800 0.000 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFG (Prop_bufg_I_O) 0.101 0.101 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=1083, unplaced) 0.800 0.901 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/hdmi_clk
FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 1.379 f i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/Q
net (fo=194, unplaced) 0.460 1.839 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_rst
FDCE f i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/CLR
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
6.735 6.735 r
PS7_X0Y0 PS7 0.000 6.735 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, unplaced) 0.000 6.735 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFG (Prop_bufg_I_O) 0.091 6.826 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.760 7.586 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.611 5.975 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, unplaced) 0.760 6.735 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFG (Prop_bufg_I_O) 0.091 6.826 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=1083, unplaced) 0.760 7.586 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
FDCE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/C
clock pessimism 0.010 7.596
clock uncertainty -0.147 7.448
FDCE (Recov_fdce_C_CLR) -0.523 6.925 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg
-------------------------------------------------------------------
required time 6.925
arrival time -1.839
-------------------------------------------------------------------
slack 5.086
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.464ns (arrival time - required time)
Source: i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
(rising edge-triggered cell FDRE clocked by mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Destination: i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/CLR
(removal check against rising-edge clock mmcm_clk_0_s {rise@0.000ns fall@3.367ns period=6.735ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (mmcm_clk_0_s rise@0.000ns - mmcm_clk_0_s rise@0.000ns)
Data Path Delay: 0.341ns (logic 0.147ns (43.121%) route 0.194ns (56.879%))
Logic Levels: 0
Clock Path Skew: 0.018ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.384ns
Source Clock Delay (SCD): 0.363ns
Clock Pessimism Removal (CPR): 0.003ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFG (Prop_bufg_I_O) 0.026 0.026 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.337 0.363 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-0.700 -0.337 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, unplaced) 0.337 -0.000 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFG (Prop_bufg_I_O) 0.026 0.026 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=1083, unplaced) 0.337 0.363 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/hdmi_clk
FDRE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.147 0.510 f i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/Q
net (fo=194, unplaced) 0.194 0.704 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_rst
FDCE f i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/CLR
------------------------------------------------------------------- -------------------
(clock mmcm_clk_0_s rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
net (fo=1, unplaced) 0.000 0.000 i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
BUFG (Prop_bufg_I_O) 0.029 0.029 r i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
net (fo=2, unplaced) 0.355 0.384 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-0.739 -0.355 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
net (fo=1, unplaced) 0.355 0.000 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
BUFG (Prop_bufg_I_O) 0.029 0.029 r i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
net (fo=1083, unplaced) 0.355 0.384 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
FDCE r i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/C
clock pessimism -0.003 0.381
FDCE (Remov_fdce_C_CLR) -0.141 0.240 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg
-------------------------------------------------------------------
required time -0.240
arrival time 0.704
-------------------------------------------------------------------
slack 0.464
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