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Analysis & Synthesis report for med_count
Mon Apr 04 17:11:18 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Failed - Mon Apr 04 17:11:18 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; med_count ;
; Top-level Entity Name ; med_count ;
; Family ; MAX7000S ;
+-----------------------------+----------------------------------------------+
+------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; med_count ; med_count ;
; Family name ; MAX7000S ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Auto ; Auto ;
; Ignore SOFT Buffers ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell ; 100 ; 100 ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+--------------------------------------------------------------+-----------------+---------------+
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------+
; med_count.vhd ; yes ; User VHDL File ; C:/Users/hp/Desktop/数电课设/shudian_medicinecount/med_count.vhd ;
; bottle_count.vhd ; yes ; User VHDL File ; C:/Users/hp/Desktop/数电课设/shudian_medicinecount/bottle_count.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Apr 04 17:11:18 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off med_count -c med_count
Info: Found 2 design units, including 1 entities, in source file med_count.vhd
Info: Found design unit 1: med_count-main
Info: Found entity 1: med_count
Info: Found 2 design units, including 1 entities, in source file bottle_count.vhd
Info: Found design unit 1: bottle_count-main
Info: Found entity 1: bottle_count
Info: Elaborating entity "med_count" for the top level hierarchy
Info: Elaborating entity "bottle_count" for hierarchy "bottle_count:A5"
Error: Node instance "A1" instantiates undefined entity "time_trans" File: C:/Users/hp/Desktop/数电课设/shudian_medicinecount/med_count.vhd Line: 75
Error: Node instance "A2" instantiates undefined entity "med_total" File: C:/Users/hp/Desktop/数电课设/shudian_medicinecount/med_count.vhd Line: 76
Error: Node instance "A3" instantiates undefined entity "control" File: C:/Users/hp/Desktop/数电课设/shudian_medicinecount/med_count.vhd Line: 81
Error: Node instance "A4" instantiates undefined entity "each_one" File: C:/Users/hp/Desktop/数电课设/shudian_medicinecount/med_count.vhd Line: 82
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 238 megabytes
Error: Processing ended: Mon Apr 04 17:11:18 2022
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:01
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