SCUBA, Version Diamond (64-bit) 3.10.0.111.2
Mon Jul 27 22:14:09 2020
  
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
  
BEGIN SCUBA Module Synthesis
  
    Issued command   : /home/yhp/data/exsoft/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_clk -lang verilog -synth lse -arch xo2c00 -type pll -fin 12 -fclkop 120 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 
    Circuit name     : pll_clk
    Module type      : pll
    Module Version   : 5.7
    Ports            : 
    Inputs       : CLKI
    Outputs      : CLKOP
    I/O buffer       : not inserted
    EDIF output      : pll_clk.edn
    Verilog output   : pll_clk.v
    Verilog template : pll_clk_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : pll_clk.srp
    Estimated Resource Usage:
  
END   SCUBA Module Synthesis