<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="step_tp" device="LCMXO2-4000HC-4MG132C" default_implementation="impl1">
    <Options/>
    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
        <Options def_top="top"/>
        <Source name="pll_clk.ipx" type="IPX_Module" type_short="IPX">
            <Options/>
        </Source>
        <Source name="top.v" type="Verilog" type_short="Verilog">
            <Options top_module="top"/>
        </Source>
        <Source name="ltc2357_master.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="divide.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="monopulse.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="auto_rst.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="step_tp.lpf" type="Logic Preference" type_short="LPF">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="step_tp1.sty"/>
</BaliProject>